1. Field of the Invention
The present invention relates to an internal voltage generator, and more particularly to, an internal voltage generator which can restrict abnormal variations of an internal voltage resulting from a leakage current generated in a driving transistor.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generator.
Referring to FIG. 1, the conventional internal voltage generator includes a comparator 100 and a PMOS driving transistor PM1. The comparator 100 compares a reference voltage Vref inputted to its negative terminal with an internal voltage Vint inputted to its positive terminal, and outputs the comparison result. The PMOS driving transistor PM1 is turned on/off according to the output signal from the comparator 100. The PMOS driving transistor PM1 has its source terminal connected to a driving voltage VDD. When the PMOS driving transistor PM1 is turned on, the PMOS driving transistor PM1 supplies the internal voltage Vint to the inside of a semiconductor device through its drain terminal. Still referring to FIG. 1, the drain terminal of the PMOS driving transistor PM1 is feedback-coupled to the positive terminal of the comparator 100.
The operation of the internal voltage generator of FIG. 1 will now be explained.
The comparator 100 compares the reference voltage Vref with the internal voltage Vint. When the internal voltage Vint is lower than the reference voltage Vref, the comparator 100 outputs a low level signal to turn on the PMOS driving transistor PM1. Accordingly, the driving voltage VDD of the source terminal is transmitted to the drain terminal, to increase the internal voltage Vint. When the increased internal voltage Vint is over the reference voltage Vref, the output from the comparator 100 has a high level, to turn off the PMOS driving transistor PM1. Therefore, increase of the internal voltage Vint is restricted. When a predetermined time elapses, the internal voltage Vint becomes lower than the reference voltage Vref, and the aforementioned procedure is repeated. As a result, power is continuously consumed in the internal voltage generator.
However, the conventional internal voltage generator has the following disadvantages.
1. Power consumption increases in the internal voltage generator due to a high speed tendency of the semiconductor device.
2. In spite of high integration of the semiconductor device, driving capability must be improved by using a large-sized driving transistor to generate a stable internal voltage.
3. As the driving voltage of the semiconductor device is lowered, a threshold voltage of the driving transistor is also lowered. When the threshold voltage is lowered, although the driving transistor must maintain a turn-off state, a leakage current is generated, to unnecessarily increase the internal voltage. The leakage current is Io*exp(Vgs−Vth)/nkT in the turn-off state. That is, when the size of the driving transistor increases and the threshold voltage decreases, the leakage current increases.